FEL: Tidy your VHDL files with a simple Perl script

One of the problems digital designers encounter while working with VHDL is that every designer seems to have his/her coding style. Though many companies enforce some coding styles, some files still entail ad-hoc tabs and spacings.

Fedora and EPEL-5 repositories include perl-Hardware-Vhdl-Tidy which helps digital designers from pulling their hairs off while working in a complex ASIC/FPGA design.

To install perl-Hardware-Vhdl-Tidy on Fedora :
# yum install perl-Hardware-Vhdl-Tidy

Below is a perl script that you can copy-paste in a file "tidyvhdl.pl" and parse your vhdl file as an argument.

#!/usr/bin/perl
use strict;
use warnings;

use IO::File;

use Hardware::Vhdl::Tidy qw/ tidy_vhdl_file /;

my $infile   = $ARGV[0];
my $tempfile = IO::File->new_tmpfile;

# -----------------------------------------------------
# Tidying original and dumping output into a temp file
# -----------------------------------------------------
tidy_vhdl_file( {
    source               => $infile,
    destination          => $tempfile,

    indent_spaces        => 4,
    tab_spaces           => 4,
    cont_spaces          => 0,
    starting_indentation => 0,
    indent_preprocessor  => 0,
    preprocessor_prefix  => '#',
} );
# -----------------------------------------------------