Closing this blog

Ever since I started blogging I was using blogger. However since the beginning of this year, there are growing number of spammers who are making my life miserable. I had to set up the comments into a moderation mode. But still spammers found a way to post comments.

Yesterday, Mirjam was talking about Wordpress and she convinced me to give it a try. I spent an hour to choose a theme and a few minutes to migrate all my blog posts and comments from blogger to wordpress.

As from now on, I will use my new blog at chitlesh.wordpress.com. If you are subscribe to this blog via RSS feeds, please from now on use this feed http://chitlesh.wordpress.com/feed/ . Sorry for the inconvenience.

While Qualcomm is eager to provide 28nm chips as from 2010, I'm eager to discover those new features of wordpress.

Using Fedora's Windows cross compilers

Last week announced the availability of Fedora 11. This new release entails Windows cross-compilers introduced by Fedora's MinGW Special Interest Group.

The aim is to eliminate duplication of work for application developers by providing a range of libraries and development tools which have already been ported to the cross-compiler environment. This means that developers will not need to recompile the application stack themselves, but can concentrate just on the changes needed to their own application.

Though this feature will interest a wide range of software developers, I believe EDA vendors will also be very interested. I will demonstrate a quick example of how to use these Windows cross-compilers.

In this demo, I will use gerbv, a gerber viewer and the example "Temperature Collector" developed by Levente Kovacs.

To install gerbv on fedora,

# yum install gerbv


The above screenshot shows gerbv compiled under a normal Linux "configure && make". Now we will compile the same gerbv for Windows.

1. Download the sources of gerbv.

2. Setup your Fedora 11 Linux

# yum install mingw32-gcc mingw32-gtk2 mingw32-crossreport mingw32-nsiswrapper wine

3. Configure Wine.

4. Extract gerbv sources.

5. Compilation of gerbv for Windows
$ cd gerbv-2.2.0
$ mingw32-configure
$ mingw32-make

The final Windows executable file of gerbv will be stored in src/.libs/ as gerbv.exe together with its DLL file, libgerbv-1.dll.

6. Launch gerbv.exe under wine

$ wine src/.libs/gerbv.exe


7. Test gerbv.exe under windows.

Under windows, extra DLLs are required and these can be downloaded from The GTK+ Project or simply from here.

The gerber files used in this example, my compiled gerbv.exe and libgerbv-1.dll can be downloaded from here.

mingw32-nsiswrapper can later be used for building automated Windows installers for distribution.

I hope this short crash course will help you. For any additional details, please join the Fedora Mingw mailing list or IRC: #fedora-mingw on FreeNode.

References:

• Fedora IRC Classroom - Using the Windows cross-compiler with Richard Jones
• Windows cross compiler Feature wiki page

A junior ASIC Guy Visits An FPGA World

The title of this blog post was copied from Harry Gries's blog post An ASIC Guy Visits An FPGA World and reflects my thoughts as a junior.

Harry's observations are oriented towards the "raw" design methodology proposed by the FPGA design tools vendors. Coming from the ASIC environment, we are heavily design methodology oriented and work hard to satisfy design tools. But in the FPGA environment, the design tools provide an even more automated work flow from frontend to backend. Physical design sometimes (depending on the size of the design) seems to take a few minutes. I have seen people even skip the entire the physical design, unless there is a violation somewhere.

I had a few FPGA projects to handoff and though they were for some different medium-sized companies, sometimes I felt that project managers and reviewers were not serious enough like in ASIC environment. I got a few remarks for my VHDL designs which sometimes coming from a senior FPGA designer shocked me. It is true as well that FPGA design was not their prime development base.

One of those remarks which till now I have not really understood the reason between it and why my reasoning was not valid. It concerned my FSMs. They had "next-state" decoding and "output" decoding into two separate VHDL processes. My reasoning which Altera's appplication notes implies will restrict the synthesis tool from sharing resources with other blocks. The remark I got, during a code review, was "I never seen that in my 12 years career, clean this". I am still eager to know what advantage will my design have while combining these two processes.

I also got the most chaotic code review experience with other FPGA designers. VHDL code review was left incomplete from my point of view and discarded parts of code review with respect to switching rates, power, ... due to lack of time. I was expecting a thorough code review for an optimal the sign-off and hand-off like I used to see with ASIC design teams.

I'm sure this is not true in every FPGA design team. What I was to say here is that during the excursion to the FPGA world, the strict discipline routine one has in ASIC environment just fades away. How quickly? I think it depends on the FPGA design team. I could even feel how disconnected the small companies are from the EDA vendors. However, I wish to get myself involved with a "real" high-performance FPGA based design team to see how discipline they are :)

While these are issues I personally encountered, I am trying to get Fedora Electronic Lab enough collaborative solutions so that small companies can at least have a decent code review, project hand-off and make FPGA designers happy.

FEL: Improving collaborative hardware development experience

One of the many faces of digital hardware design entails tracking many files to be fed to multiple EDA tools. The eventual reports or netlists are carefully analysed and logged as part of the sign-off methodology. Each company tracks these project dependent files under a certain directory structure and under a certain revision controlled system of their choice.

The development cycle Fedora Electronic Lab 12 has started. One key feature for the next Fedora 12 release will be improving "collaborative hardware development experience" on Fedora. As a test-case scenario, let's imagine 4 persons (from 4 different continents) have encountered each other using a particular social networking medium and want to engage into the development of a FPGA project.

While Fedora Electronic Lab already includes the respective simulators for digital design (VHDL/Verilog), waveforms viewers, schematic editors, PCB layout editor and Fedora's different webserver and security solutions, these 4 persons (test-case scenario) should not have any issue with the latest Fedora 11 release.

For Fedora 12, we want to ensure that these persons have adequate tools to set up a webserver dedicated for hardware design and help them improve their sign-off and code review methodologies. Hardware code review for small inexperienced companies is often misguided and ends up wasting work hours in unnecessary meetings. Designers often have mixed feelings about code reviews. Sometimes when the code review is outsourced to a third party, source codes are sent in the form of tarballs and tracked as tarballs instead of files, which this is no means an efficient way.

We are currently including an efficient and reliable code review solution into the Fedora collection. This free and opensource solution will also help create links and seamless references between bugs, tasks, changesets and files. Project coordinators will have a more realistic the overview of the on-going project and track the progress very easy with respect to different milestones and deadlines.

Coupled with Fedora's commitment in Virtualization and SELinux, hardware designers will benefit with a free and robust platform which can easily be deployed.

Fedora Electronic Lab 11 Leonidas Released

Fedora Project - This week announced the availability of Fedora 11 Leonidas and its spins. These spins provide different flavours of Fedora 11 targeting specific users and applications.

The fourth consecutive release of Fedora Electronic Lab is part of those spins, offering the best hardware design and simulation experience with opensource EDA software.


Fedora Electronic Lab 11 Leonidas provides a vibrant environment for designing and simulating ASIC design and embedded design. The opensource EDA solutions are composed to satify high-end mixed-signal hardware design flows from design specification to final project handoff. This release comprises Perl modules to facilitate both design, HDL code generation and brings additional support for Engineering Change Order (ECO). After post chip fabrication, evaluation boards of those chips can also be designed.

Advantages

• Deployable in both development and production environments.
• No kernel patches are required, making it easy to deploy and use.
• No licenses required and it is free.

Key Highlights

Existing RPM packages were updated improve design experience in terms of development time and debugging. The key highlights of the major development items puts the quality barrier higher than the previous releases:

• Perl modules to extend vhdl and verilog support. These Perl modules together with gtkwave improves chip testing support.
• Perl parsers for VHDL, Verilog and SystemC.
• Introduced collaborative development solutions.
• Introduction of Verilog-AMS modeling into ngspice.
• Improved VHDL debugging support with gcov.
• Improved support for re-usable HDL packages as IP core.
• Improved PLI support on both iverilog and ghdl
• Introduction of C-based methodologies for HDL testbenches and models.
• Improved co-simulation based hardware design.
• Introduction of design tools for DSP design flow.

Eclipse, the comprehensive Integrated Development Environment (IDE) for embedded systems is also part of the collection. This IDE is included for the first time on the Livedvd (but available since a long time on Fedora repositories) entails plugins for C++, Perl and Version Control systems (CVS,GIT,SVN).

Download the Fedora Electronic Lab 11 flyer for additional details.


Userbase

• Students/researchers
• Lecturers
• Analog/Digital/Mixed Signal hardware designers (even Test engineers)
• System Electronic Engineers
• Project Coordinators
• New opensource EDA developers
• Field application engineers

About Fedora Electronic Lab

Fedora Electronic Lab is Fedora's high-end hardware design and simulation platform. This platform provides different hardware design flows based on the semiconductor industry's current trend. FEL maps in new design, simulation and verification methodologies with opensource EDA software.

For more information and download, go to website.

Hello edacafe

It is with great pleasure that today I’ve a featured blog on EDACafe. My name is Chitlesh Goorah. I will be exposing different opensource solutions which will interest both EDA engineers and ASIC designers.

Some of you may know me from my work behind Fedora Electronic Lab. For about three years now, we are proposing an opensource ASIC design and simulation platform, which is fairly well accepted by many universities around the world. We are working closely with many upstream projects such as gEDA, veripool, open circuit design, … in order to ensure interoperability between our solutions.

At the same time, Fedora developers are introducing Windows cross-compilers for the next version. Thereby, EDA vendors can also use Fedora or entreprise-class distribution such as RHEL or CentOS as a development ground for their products.

Later, I will introduce other features such as virtualisation, mass deployment, various design handoff checking facilities, … etc each accompanying with at least an example. Many designers and CAD engineers are already using opensource tools such as Vi, Emacs, svn, … I am looking forward to read your comments on my next posts.

FEL: Emacs, Verilog-mode, dinotrace

I have just pushed dinotrace to Fedora stable repositories. This will elevate the digital design experience for Emacs users.

Fedora users can soon install it with:

# yum install dinotrace emacs-dinotrace

I will briefly describe some features of this co-design possibility which dinotrace and verilog-mode provides on this blog post. However for more technical details, consult the manual.


1: Dinotrace is a waveform viewer which read .vcd files, generated by ghdl or iverilog. It includes a .el file for emacs which enables the designer to interact with the signals on dinotrace via emacs.

To load dinotrace-mode on emacs:
Alt-x dinotrace-mode

To load verilog-mode on emacs:
Alt-x verilog-mode

2: Verilog-mode provides designer with context-sensitive highlighting, auto indenting, and macro expansion capabilities to greatly reduce Verilog coding time. It also prevents additional human errors while coding. I will describe a few macro-expansion capabilities below.

3: Signal highlighting. Both Emacs and dinotrace can share the same colour to represent signals.

4: With annotation feature, the values of the signals with respect to the cursors' position on the waveform viewer is annotated on the Emacs. This will help designers to debug their complex designs efficiently.

The above screenshot shows a simple frequency divider coded with verilog-mode macros and the same verilog after the macros were automatically expanded by Emacs. For more details about other macros, consult the verilog-mode manual. Happy design on Fedora.

FEL on OpenCores Newsletter May 2009

In today's OpenCores newsletter May 2009, FEL is listed among OpenCores's open source EDA tools

FEL: Tidy your VHDL files with a simple Perl script

One of the problems digital designers encounter while working with VHDL is that every designer seems to have his/her coding style. Though many companies enforce some coding styles, some files still entail ad-hoc tabs and spacings.

Fedora and EPEL-5 repositories include perl-Hardware-Vhdl-Tidy which helps digital designers from pulling their hairs off while working in a complex ASIC/FPGA design.

To install perl-Hardware-Vhdl-Tidy on Fedora :
# yum install perl-Hardware-Vhdl-Tidy

Below is a perl script that you can copy-paste in a file "tidyvhdl.pl" and parse your vhdl file as an argument.

#!/usr/bin/perl
use strict;
use warnings;

use IO::File;

use Hardware::Vhdl::Tidy qw/ tidy_vhdl_file /;

my $infile   = $ARGV[0];
my $tempfile = IO::File->new_tmpfile;

# -----------------------------------------------------
# Tidying original and dumping output into a temp file
# -----------------------------------------------------
tidy_vhdl_file( {
    source               => $infile,
    destination          => $tempfile,

    indent_spaces        => 4,
    tab_spaces           => 4,
    cont_spaces          => 0,
    starting_indentation => 0,
    indent_preprocessor  => 0,
    preprocessor_prefix  => '#',
} );
# -----------------------------------------------------

FEL's Events in May

Our Fedora ambassador team has dedicated their time and effort to introduce you new features coming with Fedora 11. They have been organizing and attending several events in your locality and in your local language.

These ambassadors recently gave talks and demonstrations about Fedora Electronic Lab in Greece and India.

8 May 2009 - FOSSCOMM 2009 - Larissa, Greece By Kostas Antonakoglou
Fedora Electronic Lab was introduced and a work flow demonstration was conducted to show how electronic design can be achieved efficiently with opensource software. -- Blog Report

14-15 May 2009 at Dr. B.C Roy Engineering College, India By Rangeen Basu, Subhodip Biswas, Arindam Ghosh, Ratnadeep Debnath and Kishan Goyal
FEL was deployed under 30 computers to demonstrate gsim85, Ktechlab, octave, piklab, gresistor, drawtiming, ghdl, ... FEL LiveDVDs were distributed freely.. - -- Blog Report 1 -- Blog Report 2 -- Blog Report 3 -- Blog Report 4 -- Blog Report 5

On the 31 May 2009, in Malaysia, at the "Red Hat brings you Fedora Activity Day During MSC Malaysia Open Source Conference 2009", Mohammad Razi will give an overview about Fedora Electronic Lab.

Verilog::Language 3.210 pushed to Fedora stable

Verilog::Language perl module was just pushed to Fedora stable repositories. It is just a matter of time till it will hit your local mirrors.

Among the key features:

• Verilog::Parser, SigParser and Netlist now support SystemVerilog.
• Verilog::SigParser's signal_decl and funcsignal callbacks no longer work. They are replaced by the "var" callback.
• Added Verilog::SigParser program and endprogram callbacks.
• Calling Verilog::SigParser->new now requires a symbol_table parameter, if multiple modules are to be parsed as part of one compilation unit.
• Netlist::Port->type accessor is renamed data_type. [Horia Toma]
• Netlist::Net->type accessor is split into data_type, decl_type and net_type accessors.
• Netlist::Module->ports_ordered now returns objects. [Horia Toma]
• Added Netlist::Interface and related accessors.
• Added Netlist::Module->keyword accessor, and use it for "program"s.
• Fix logic MSBs not being reported in 3.200 beta. [Horia Toma]
• Fixes for numerous parsing and netlists errors

Xilinx-icarus verilog : post synthesis simulation

Earlier, I've described how you could do post synthesis simulation with ghdl from a generated xilinx-based vhdl netlist. Below, you can now find how simulate with icarus verilog if that netlist was to be verilog-based:

# yum install iverilog

# -------------------------------------------------------------
postsim:
 iverilog -Wall \
   -y $(XILINXCADROOT)/verilog/src/unisims \
   -y $(XILINXCADROOR)/verilog/src/XilinxCoreLib \
   $(PROJECT)_synthesis.v $(PROJECT)_tb.v -o $(PROJECT).bin
 vvp $(PROJECT).bin
#---------------------------------------------------------------

If you like automating your verilog-based digital design flow, Fedora provides additional perl scripts for Verilog (as well for VHDL) to help you sign off different stages of your design flow. Learn more about those Perl modules by:

# yum search perl-Verilog*

# rpm -qd PACKAGE

We would like to know if you are encountering any difficulties in your custom design flow with Fedora Electronic Lab, maybe we can smooth the edges for you.

With upcoming Fedora 11, we have provided enough solutions to harden your ASIC handoff checklist.

EDA: Temperature Collector

Levente Kovacs shares with us his Temperature Collector project, which he achieved with gEDA/gaf tools. Below you can see the screenshots on pcb and gerbv respectively:



You too can share the screenshots of your designs with opensource EDA software.

Fedora FEL 11 Preview features

Fedora 11 release is scheduled for 26 May 2009.

Fedora Electronic Lab has gained some valuable Perl modules for digital design automation which improve HDL verifications and debugging. The release notes of Fedora FEL 11 preview can be found here. FEL11 development is now frozen and FEL12 development items are being discussed.

Updates of the existing RPM packages will improve design experience in terms of development time and debugging. The key highlights of the major development items puts the quality barrier higher than the previous releases:

• Perl modules to extend vhdl and verilog support. These Perl modules together with rawhide's gtkwave improves chip testing support.
• Introduction of Verilog-AMS modeling into ngspice.
• Improved VHDL debugging support with gcov.
• Improved support for re-usable HDL packages as IP core.
• Improved PLI support on both iverilog and ghdl
• Introduction of C-based methodologies for HDL testbenches and models.
• Improved co-simulation based hardware design.
• Introduction of design tools for DSP design flow.

Episode 4: I speak dutch fluently too?

Well, if the waiter did not understand Jeroen's dutch (though he is a dutch), then all I can deduce are either:

• I speak dutch fluently too, or
• Jeroen is not really a dutch or hides a big secret we are not aware, aside steak tartar.

Episode 3 : Ordering something in Dutch
Episode 2 : Under the clouds and winds of Amsterdam
Episode 1 : Social butterfly

Xilinx-GHDL : post synthesis simulation

Those who like ghdl and gtkwave frequently ask the same question while working with Xilinx FPGAs. "How can one do post synthesis with unisim libraries ?"

Below you will find part of a makefile which automates this post synthesis simulation with ghdl and gtkwave. I assume that you have already installed the xilinx webpack by yourself. Fedora 10 has the latest gtkwave version with tcl and tab support to improve your verification methodologies. Happy design on your Fedora.

  
# ----------------------------------------------------
PROJECT       = cst299
XILINXCADROOT = /opt/xilinx/ISE/10.1.03_K.39/ISE

UNISIMS       = $(XILINXCADROOT)/vhdl/src/unisims

postsyn: libunisim postsyn_sub compileTb runTb

libunisim:
 rm -rf unisim && mkdir -p unisim
 ghdl -a --work=unisim --workdir=unisim \
  --ieee=synopsys -fexplicit     \
  $(UNISIMS)/unisim_VCOMP.vhd    \
  $(UNISIMS)/unisim_VPKG.vhd     \
  $(UNISIMS)/unisim_SMODEL.vhd   \
  $(UNISIMS)/unisim_virtex5_SMODEL.vhd
 # http://ghdl.free.fr/ghdl/Using-vendor-libraries.html
 cp -p $(UNISIMS)/unisim_VITAL.vhd unisim_VITAL.vhd
 sed -i  -e "s|variable Write_A_Write_B|--variable Write_A_Write_B|" \
  -e "s|variable Read_A_Write_B|--variable Read_A_Write_B|"   \
  -e "s|variable Write_A_Read_B|--variable Write_A_Read_B|"   \
  -e "s|variable Write_B_Write_A|--variable Write_B_Write_A|" \
  -e "s|variable Read_B_Write_A|--variable Read_B_Write_A|"   \
  -e "s|variable Write_B_Read_A|--variable Write_B_Read_A|"   \
  unisim_VITAL.vhd
 ghdl -a --work=unisim --workdir=unisim \
  --ieee=synopsys -fexplicit     \
  --warn-no-vital-generic unisim_VITAL.vhd

postsyn_sub:
 rm -rf work && mkdir -p work
 ghdl -a --work=work -Punisim --workdir=work \
  --ieee=synopsys -fexplicit \
  $(PROJECT)\_synthesis.vhd

compileTb:
 ghdl -a --work=work -Punisim --workdir=work \
  --ieee=synopsys -fexplicit \
  --warn-no-vital-generic $(PROJECT)\_tb.vhd
 # Compile Testbench
 ghdl -m --work=work -Punisim --workdir=work \
  --ieee=synopsys -fexplicit \
  --warn-no-vital-generic $(PROJECT)\_tb

runTb:
 # Run Testbench
 ghdl -r --workdir=work \
  $(PROJECT)\_tb --vcd=$(PROJECT)_postsyn.vcd \
  --stop-time=200ns
#---------------------------------------------------------------
Then use gtkwave to view the waveform.

Engineers should stage a patent strike

Rick Merritt shares his opinion: Engineers should stage a patent strike. He thinks it's time for design engineers to stage an intellectual property strike.

As far as I know, some companies give bonus to Analog ASIC engineers if they initiated and maintain IP for the company. But at the same time, during this financial crisis, some companies have cancelled such bonus.

Under the clouds and winds of Amsterdam

Last saturday, Mirjam and I spent the day visiting Amsterdam. We believe that Amsterdam is beautiful if there is sunshine.

We also had a cheerful dinner with Max before returning back to Antwerp. Just to support Max's paragraphon Xzibit, Mirjam and I saw a poster of Xzibit's concert in Antwerp.

last perl-Verilog bug fix release 3.121

A bug fix release with some minor feature additions was pushed to F-9, F-10 and EL-5 repositories

These minor feature additions are

• Make cell names unique when duplicate cells encountered. [Paul Janson]
• Remove unused parameter in exit_if_error. [Paul Janson]
• Fix modported instance name passed to SigParser::instant callback.

WilsonSnyder was already created a GIT 3.200 branch, which adds SystemVerilog support.

jobless

I lost my job today :(